Pranjal Ahluwalia
Software engineer
Systems Engineer
at Infosys Ltd. , Hyderabad,
India
Systems Engineer
Employee Id - 713139
February 2016 - present
Currently for the past 0.2 year involved in offshore projects at Infosys Hyderabd. My unit at Infosys is financial services.
Systems Engineer Trainee
September 2015 - January 2016
2 months generic training in Python and SQL server from Infosys Mysore campus. 2 months technology training in JAVA (J2EE) comprising hiberate API and JSF for UI.
HPES Internship program
July-August 2014
Electronic Voting Machine: The programming is done in C and based on that the count of different candidates is increased.Key Learnings: Worked on Atmega-128A, wireless module and establish communicationbetween computer and hardware kit provided (USB-UART and I2C), used Docklite and AVRstudio software and interfaced LCD, temperature sensor and WSN with microcontroller.
Summer training program from ONGC firm
June-July 2014
In this project I got holistic picture of the ONGC Network, studied network layers/models and network topologies. Overview of network instructions, Ping and Telnet. On site visit to satellite earth station and learned how data is received and transmitted circuits are implemented in the real time basis.
Winter training program from KHODRI POWER HOUSE
January-2014
Overview of different setups in a electricity generation power house, on site visit to control room and Dam; learned how electricity is generated and transmitted in the real time environment.
Graphic Era University
2011-2015
Bachelors of Technology in Electronics And Communication
S.G.R.R Public School
2009-2011
Intermediate from CBSE board Dehradun in the year 2011.
High school from CBSE board Dehradun in the year 2009.
RESUME
Professional
info
Work
experience
Education
Skills
Xilinx (ISE 10.2),
Virtuoso (Cadence)
Model Sim(Mentor Graphics)
Basics of MATLAB
Eclipse IDE
Proteus
Turbo C
Software testing (Junit test tool)
Hibernate API
Languages
C
x85 and x86 assembly Language
C++
Java(J2EE)
SQL/PL SQL
OS (Windows)
RDBMS
CSS & HTML for UI
Python
VHDL
Achievements
Research Paper
At International Journal Of Science Technology & Management (ISSN 2394-1537), Volume 04, Issue 01, January 2015
TITLE: PERFORMANCE COMPARISON OF DIGITAL GATES USING CMOS AND PASS TRANSISTOR LOGIC USING CADENCE VIRTUOSO
PAPER ID: IJSTM/December/2014/188)
SERIAL NO: 6