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Pranjal Ahluwalia
Software engineer
LATEST PROJECTS
Electronic payment portal
Training project to add a functionality in an application giving admin of the website to approve new users including the service providers and the services. The website was running over antbuild in Java platform.
Electronic payment portal
Maintainance project in training to fix the buggs in an application according to the tickets received. The website was running over antbuild in Java platform.
Performance Comparison of Digital Cell Library Using Cmos and Pass Logic (Feb 2015- June
2015):
A Mechanism of reducing chip size by innovative logical design.Pass transistor adiabatic logic and mechanism for different circuits were studied. The technique was demonstrated superior to conventional CMOS design in power savings by simulating 1-bit Full Adder, 1:4 De-Mux etc. in Cadence Virtuoso at a broad
frequency spectrum. RTL coding was done on Xilinx.
To see more or discuss possible work let's talk >>
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